SN74LVTH374DBR
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Lifecycle Status | ACTIVE (Last Updated: 5 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-SSOP (0.209, 5.30mm Width) |
| Number of Pins | 20 |
| Weight | 156.687814mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Cut Tape (CT) |
| Series | 74LVTH |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVTH374 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Operating Supply Voltage | 3.3V |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 2.7V |
| Number of Circuits | 8 |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Output Current | 64mA |
| Number of Bits | 8 |
| Clock Frequency | 150MHz |
| Propagation Delay | 2.9 ns |
| Turn On Delay Time | 2.9 ns |
| Family | LVT |
| Logic Function | D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Max I(ol) | 0.064 A |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Power Supply Current-Max (ICC) | 5mA |
| Number of Output Lines | 3 |
| Count Direction | UNIDIRECTIONAL |
| Clock Edge Trigger Type | Positive Edge |
| Translation | N/A |
| Height | 2mm |
| Length | 7.2mm |
| Width | 5.3mm |
| Thickness | 1.95mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVTH374DBR Overview
It is packaged in the way of 20-SSOP (0.209, 5.30mm Width). The Cut Tape (CT)package contains it. Currently, the output is configured to use Tri-State, Non-Inverted. It is configured with a trigger that uses a value of Positive Edge. The electronic part is mounted in the way of Surface Mount. A voltage of 2.7V~3.6Vis required for its operation. It is operating at -40°C~85°C TA. It belongs to the type D-Typeof flip flops. In FPGA terms, D flip flop is a type of 74LVTHseries FPGA. You should not exceed 150MHzin its output frequency. A total of 1elements are contained within it. This process consumes 190μA quiescents. A total of 20 terminations have been made. The object belongs to the 74LVTH374 family. A voltage of 3.3V is used to power it. JK flip flop input capacitance is 3pF farads. This D flip flop belongs to the family of LVT. This electronic part is mounted in the way of Surface Mount. 20pins are included in its design. The clock edge trigger type for this device is Positive Edge. The part is included in FF/Latches. It is designed with a number of bits of 8. Normal operation requires a supply voltage (Vsup) above 2.7V. Its superior flexibility is attributed to its use of 8 circuits. In view of its reliability, this D flip flop is a good fit for TR. A total of 2ports are embedded in the D flip flop. A high level of efficiency can be achieved by maintaining the supply voltage at 3.3V. With an output current of 64mA, this device offers maximum design flexibility. To operate, the chip has a total of 3 output lines.
SN74LVTH374DBR Features
Cut Tape (CT) package
74LVTH series
20 pins
8 Bits
SN74LVTH374DBR Applications
There are a lot of Texas Instruments SN74LVTH374DBR Flip Flops applications.
- Control circuits
- Latch-up performance
- ESD performance
- Data Synchronizers
- Count Modes
- Patented noise
- Load Control
- ESD protection
- Supports Live Insertion
- Individual Asynchronous Resets
