SN74LVTH574DWR

2.7V~3.6V 150MHz 8 Bit D-Type Flip Flop DUAL 74LVTH574 20 Pins 190μA 74LVTH Series 20-SOIC (0.295, 7.50mm Width)

Manufacturer: Texas Instruments
Nocochips NO: 815-SN74LVTH574DWR
Package: 20-SOIC (0.295, 7.50mm Width)
Datasheet: PDF
Stock: 425
Description: 2.7V~3.6V 150MHz 8 Bit D-Type Flip Flop DUAL 74LVTH574 20 Pins 190μA 74LVTH Series 20-SOIC (0.295, 7.50mm Width)(Kg)

Details

Tags

Parameters
Factory Lead Time	1 Week
Lifecycle Status	ACTIVE (Last Updated: 2 days ago)
Contact Plating	Gold
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	20-SOIC (0.295, 7.50mm Width)
Number of Pins	20
Weight	500.709277mg
Operating Temperature	-40°C~85°C TA
Packaging	Tape & Reel (TR)
Series	74LVTH
JESD-609 Code	e4
Pbfree Code	yes
Part Status	Active
Moisture Sensitivity Level (MSL)	1 (Unlimited)
Number of Terminations	20
ECCN Code	EAR99
Type	D-Type
Subcategory	FF/Latches
Packing Method	TR
Technology	BICMOS
Voltage - Supply	2.7V~3.6V
Terminal Position	DUAL
Terminal Form	GULL WING
Peak Reflow Temperature (Cel)	260
Supply Voltage	3.3V
Base Part Number	74LVTH574
Function	Standard
Output Type	Tri-State, Non-Inverted
Operating Supply Voltage	3.3V
Number of Elements	1
Polarity	Non-Inverting
Supply Voltage-Min (Vsup)	2.7V
Number of Circuits	8
Load Capacitance	50pF
Number of Ports	2
Output Current	64mA
Number of Bits	8
Clock Frequency	150MHz
Propagation Delay	3 ns
Quiescent Current	5mA
Turn On Delay Time	3 ns
Family	LVT
Logic Function	D-Type, Flip-Flop
Current - Quiescent (Iq)	190μA
Current - Output High, Low	32mA 64mA
Max I(ol)	0.064 A
Max Propagation Delay @ V, Max CL	4.5ns @ 3.3V, 50pF
Prop. Delay@Nom-Sup	4.5 ns
Trigger Type	Positive Edge
Input Capacitance	3pF
Number of Output Lines	3
Count Direction	UNIDIRECTIONAL
Clock Edge Trigger Type	Positive Edge
Height	2.65mm
Length	12.8mm
Width	7.5mm
Thickness	2.35mm
Radiation Hardening	No
RoHS Status	ROHS3 Compliant
Lead Free	Lead Free

SN74LVTH574DWR Overview

It is embeded in 20-SOIC (0.295, 7.50mm Width) case. A package named Tape & Reel (TR)includes it. T flip flop is configured with an output of Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. A 2.7V~3.6Vsupply voltage is required for it to operate. Temperature is set to -40°C~85°C TA. D-Typeis the type of this D latch. The FPGA belongs to the 74LVTH series. There should be no greater frequency than 150MHzon its output. There are 1 elements in it. It consumes 190μA of quiescent In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. You can search similar parts based on 74LVTH574. Power is provided by a 3.3V supply. The input capacitance of this JK flip flopis 3pF farads. The electronic device belongs to the LVTfamily. There is an electronic part mounted in the way of Surface Mount. With its 20pins, it is designed to work with most electronic flip flops. This device exhibits a clock edge trigger type of Positive Edge. The part is included in FF/Latches. This flip flop is designed with 8 Bits. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 2.7V. Despite its superior flexibility, it relies on 8 circuits to achieve it. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. The flip flop has 2embedded ports. For high efficiency, the supply voltage should be kept at 3.3V. In addition to its maximum design flexibility, the output current of the T flip flop is 64mA. It has 3 output lines to operate. Despite external influences, it consumes 5mAof quiescent current.