Parameters |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
84-LCC (J-Lead) |
Number of Pins |
84 |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Tube |
Published |
1996 |
Series |
XC9500 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
Number of Terminations |
84 |
ECCN Code |
EAR99 |
Additional Feature |
YES |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
QUAD |
Terminal Form |
J BEND |
Peak Reflow Temperature (Cel) |
225 |
Supply Voltage |
5V |
Terminal Pitch |
1.27mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Base Part Number |
XC95108 |
Pin Count |
84 |
Operating Supply Voltage |
5V |
Programmable Type |
In System Programmable (min 10K program/erase cycles) |
Number of I/O |
69 |
Memory Type |
FLASH |
Propagation Delay |
15 ns |
Number of Logic Elements/Cells |
8 |
Number of Gates |
2400 |
Max Frequency |
55.6MHz |
Speed Grade |
15 |
Output Function |
MACROCELL |
Number of Macro Cells |
108 |
JTAG BST |
YES |
Voltage Supply - Internal |
4.5V~5.5V |
Number of Logic Elements/Blocks |
6 |
Radiation Hardening |
No |
RoHS Status |
Non-RoHS Compliant |
Lead Free |
Contains Lead |
XC95108-15PC84I Overview
There are 108 macro cells, which are cells in a mobile phone network that provides radio coverage served by a high-power cell site (tower, antenna or mast).The item is packaged with 84-LCC (J-Lead).The device is programmed with 69 I/O ports.Devices are programmed with terminations of [0].There is a QUADterminal position on the electrical part in question.It is powered by a voltage of 5V volts.There is a part included in Programmable Logic Devices.As a result, it is packaged as Tube.Ensure its reliability by operating at [0].It is mounted in the way of Surface Mount.It is a type of FPGA belonging to the XC9500 series.Chips are programmed with 84 pins.This device also displays [0].In accordance with the [0], its related parts are listed.2400gates are devices that serve as building blocks for digital circuits.If high efficiency is to be achieved, the supply voltage should be maintained at [0].It is recommended to store data in [0].This device is mounted by Surface Mount.The pins are [0].This logic block consists of 6logic elements.It is important to make sure that the maximum frequency is less than 55.6MHz.A fundamental building block of logic consists of 8logic elements/cells.
XC95108-15PC84I Features
84-LCC (J-Lead) package
69 I/Os
The operating temperature of -40°C~85°C TA
84 pin count
84 pins
XC95108-15PC84I Applications
There are a lot of Xilinx Inc. XC95108-15PC84I CPLDs applications.
- Software Configuration of Add-In Boards
- Bootloaders for FPGAs
- Voltage level translation
- Protection relays
- State machine control
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- Power up sequencing
- Power automation
- Multiple Clock Source Selection
- SUPERVISORY FUNCTION (LVD AND WATCHDOG)