XC95108-20PQG160I
| Parameters | |
|---|---|
| Package / Case | PQFP |
| Surface Mount | YES |
| Number of Pins | 160 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 160 |
| ECCN Code | EAR99 |
| Terminal Finish | Matte Tin (Sn) |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | -40°C |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 160 |
| Operating Supply Voltage | 5V |
| Temperature Grade | INDUSTRIAL |
| Number of I/O | 108 |
| Memory Type | FLASH |
| Propagation Delay | 20 ns |
| Frequency (Max) | 50MHz |
| Number of Logic Blocks (LABs) | 8 |
| Speed Grade | 20 |
| Output Function | MACROCELL |
| Number of Macro Cells | 108 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 4.1mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
XC95108-20PQG160I Overview
There are 108 macro cells in the network, which are high-power cell sites that provide radio coverage (tower, antenna, or mast) for a mobile phone network.The product is contained in a PQFP package.It is equipped with 108I/O ports.There are 160 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.Its terminal position is QUAD.Power is supplied by a voltage of 5V volts.This part is included in Programmable Logic Devices.There are 160 pins on the chip.When using this device, YESis also available.If high efficiency is desired, the supply voltage should be kept at [0].It is recommended that data be stored in [0].The device is designed with pins [0].It is recommended that the operating temperature exceeds -40°C.Temperatures should not exceed 85°C.There are 8logic blocks (LABs) that make up its basic building block.The maximal frequency should be lower than 50MHz.
XC95108-20PQG160I Features
PQFP package
108 I/Os
160 pin count
160 pins
8 logic blocks (LABs)
XC95108-20PQG160I Applications
There are a lot of Xilinx XC95108-20PQG160I CPLDs applications.
- I/O PORTS (MCU MODULE)
- ANALOG-TO-DIGITAL CONVERTOR (ADC)
- Software-Driven Hardware Configuration
- Configurable Addressing of I/O Boards
- Custom shift registers
- Storage Cards and Storage Racks
- ToR/Aggregation/Core Switch and Router
- Digital designs
- Protection relays
- PULSE WIDTH MODULATION (PWM)
