XC95144XV-5CS144C
| Parameters | |
|---|---|
| Surface Mount | YES |
| Number of Pins | 144 |
| JESD-609 Code | e0 |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 144 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 2.5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 144 |
| Operating Supply Voltage | 2.5V |
| Supply Voltage-Max (Vsup) | 2.62V |
| Temperature Grade | COMMERCIAL |
| Number of I/O | 117 |
| Memory Type | FLASH |
| Propagation Delay | 5 ns |
| Turn On Delay Time | 5 ns |
| Frequency (Max) | 222.2MHz |
| Organization | 0 DEDICATED INPUTS, 117 I/O |
| Number of Logic Blocks (LABs) | 8 |
| Speed Grade | 5 |
| Output Function | MACROCELL |
| Number of Macro Cells | 144 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 1.2mm |
| Length | 12mm |
| Width | 12mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
XC95144XV-5CS144C Overview
Currently, there are 144 macro cells, which are low-power cell sites (towers, antennas, masts) that serve as radio coverage.As you can see, this device has 117 I/O ports programmed into it.There is a 144terminations set on devices.There is a BOTTOMterminal position on the electrical part in question.Power is provided by a supply voltage of 2.5V volts.This part is in the family [0].A chip with 144pins is programmed.This device also displays [0].In order to maintain high efficiency, the supply voltage should be maintained at [0].For data storage, FLASHis adopted.The 144pins are designed into the board.Vsup reaches 2.62Vas the maximum supply voltage.It is recommended that the operating temperature be greater than 0°C.It is recommended that the operating temperature be below 70°C.Its basic building block is composed of 8 logic blocks (LABs).A maximum frequency of less than 222.2MHzis recommended.
XC95144XV-5CS144C Features
117 I/Os
144 pin count
144 pins
8 logic blocks (LABs)
XC95144XV-5CS144C Applications
There are a lot of Xilinx XC95144XV-5CS144C CPLDs applications.
- Handheld digital devices
- Custom shift registers
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- Dedicated input registers
- Power up sequencing
- POWER-SAVING MODES
- D/T registers and latches
- Page register
- ROM patching
- Digital systems
