XC95288-15BGG352I
| Parameters | |
|---|---|
| Surface Mount | YES |
| Published | 1996 |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Discontinued |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 352 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 352 |
| JESD-30 Code | S-PBGA-B352 |
| Qualification Status | Not Qualified |
| Operating Temperature (Min) | -40°C |
| Operating Supply Voltage | 5V |
| Temperature Grade | INDUSTRIAL |
| Number of I/O | 192 |
| Clock Frequency | 55.6MHz |
| Propagation Delay | 15 ns |
| Organization | 0 DEDICATED INPUTS, 192 I/O |
| Programmable Logic Type | FLASH PLD |
| Number of Logic Blocks (LABs) | 8 |
| Output Function | MACROCELL |
| Height Seated (Max) | 1.7mm |
| Length | 35mm |
| Width | 35mm |
| RoHS Status | Non-RoHS Compliant |
XC95288-15BGG352I Overview
As a result, it has 192 I/O ports programmed.It is programmed to terminate devices at [0].This electrical component has a terminal position of 0.Power is supplied by a voltage of 5V volts.352pins are programmed on the chip.Optimal efficiency requires a supply voltage of [0].There are 8logic blocks (LABs) that make up its basic building block.This device should not have an clock frequency greater than 55.6MHz.Programmable logic types can be divided into FLASH PLD.Temperatures should be maintained at least at [0].
XC95288-15BGG352I Features
192 I/Os
352 pin count
8 logic blocks (LABs)
XC95288-15BGG352I Applications
There are a lot of Xilinx XC95288-15BGG352I CPLDs applications.
- Power automation
- Address decoders
- ROM patching
- I2C BUS INTERFACE
- Digital multiplexers
- ToR/Aggregation/Core Switch and Router
- Storage Cards and Storage Racks
- PULSE WIDTH MODULATION (PWM)
- ON-CHIP OSCILLATOR CIRCUIT
- Power up sequencing
