Parameters |
Number of Logic Blocks (LABs) |
24 |
Speed Grade |
12 |
Output Function |
MACROCELL |
Number of Macro Cells |
384 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
2.5mm |
Length |
23mm |
Width |
23mm |
Radiation Hardening |
No |
RoHS Status |
RoHS Compliant |
Package / Case |
FBGA |
Surface Mount |
YES |
JESD-609 Code |
e1 |
Pbfree Code |
yes |
Moisture Sensitivity Level (MSL) |
3 |
Number of Terminations |
324 |
ECCN Code |
3A991.D |
Terminal Finish |
Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) |
Max Operating Temperature |
85°C |
Min Operating Temperature |
-40°C |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
250 |
Supply Voltage |
3.3V |
Terminal Pitch |
1mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
324 |
Operating Supply Voltage |
3.3V |
Supply Voltage-Max (Vsup) |
3.6V |
Temperature Grade |
INDUSTRIAL |
Number of I/O |
220 |
Memory Type |
EEPROM |
Propagation Delay |
12 ns |
Frequency (Max) |
83MHz |
Organization |
0 DEDICATED INPUTS, 220 I/O |
Programmable Logic Type |
EE PLD |
XCR3384XL-12FGG324I Overview
This network has 384macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).You can find it in package [0].The device is programmed with 220 I/O ports.The termination of a device is set to [0].The terminal position of this electrical part is BOTTOM, which serves as an important access point for passengers or freight.The device is powered by a voltage of 3.3V volts.The part is included in Programmable Logic Devices.It is programmed with 324 pins.It is also characterized by YES.The supply voltage should be maintained at 3.3V for high efficiency.EEPROM is adopted for storing data.In this case, the maximum supply voltage (Vsup) reaches 3.6V.Operating temperatures should be higher than -40°C.Ideally, the operating temperature should be below 85°C.In total, it contains 24 logic blocks (LABs).The maximum frequency should not exceed 83MHz.There is a type of programmable logic called EE PLD.
XCR3384XL-12FGG324I Features
FBGA package
220 I/Os
324 pin count
24 logic blocks (LABs)
XCR3384XL-12FGG324I Applications
There are a lot of Xilinx XCR3384XL-12FGG324I CPLDs applications.
- Bootloaders for FPGAs
- ToR/Aggregation/Core Switch and Router
- Power automation
- Timing control
- LED Lighting systems
- Battery operated portable devices
- Pattern recognition
- SUPERVISORY FUNCTION (LVD AND WATCHDOG)
- POWER-SAVING MODES
- Reset swapping