XCR3512XL-12FGG324I
| Parameters | |
|---|---|
| Factory Lead Time | 1 Week |
| Mount | Surface Mount |
| Package / Case | FBGA |
| Number of Pins | 324 |
| Published | 1996 |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 324 |
| ECCN Code | 3A991.D |
| Terminal Finish | Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | -40°C |
| Additional Feature | YES |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 250 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 324 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 3.3V |
| Supply Voltage-Max (Vsup) | 3.6V |
| Temperature Grade | INDUSTRIAL |
| Number of I/O | 260 |
| Memory Type | EEPROM |
| Propagation Delay | 12 ns |
| Frequency (Max) | 77MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 12000 |
| Number of Logic Blocks (LABs) | 32 |
| Speed Grade | 12 |
| Output Function | MACROCELL |
| Number of Macro Cells | 512 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 2.5mm |
| Length | 23mm |
| Width | 23mm |
| RoHS Status | RoHS Compliant |
XCR3512XL-12FGG324I Overview
Currently, there are 512 macro cells, which are low-power cell sites (towers, antennas, masts) that serve as radio coverage.You can find it in package [0].It is equipped with 260I/O ports.It is programmed that device terminations will be 324 .This electrical component has a terminal position of 0.Power is supplied by a voltage of 3.3V volts.It is included in Programmable Logic Devices.It is equipped with 324 pin count.It is also possible to find YESwhen using this device.12000gates are used to construct digital circuits.High efficiency requires a voltage supply of [0].In this case, EEPROMwill be used to store the data.It is mounted by Surface Mount.The 324pins are designed into the board.Supply voltage (Vsup) reaches a maximum of 3.6V.In order to operate, the temperature should be higher than -40°C.A temperature lower than 85°Cis recommended for operation.In its simplest form, it consists of 32 logic blocks (LABs).There should be a lower maximum frequency than 77MHz.This kind of FPGA is composed of EE PLD.
XCR3512XL-12FGG324I Features
FBGA package
260 I/Os
324 pin count
324 pins
32 logic blocks (LABs)
XCR3512XL-12FGG324I Applications
There are a lot of Xilinx XCR3512XL-12FGG324I CPLDs applications.
- Synchronous or asynchronous mode
- Multiple Clock Source Selection
- Portable digital devices
- Timing control
- Field programmable gate
- Custom state machines
- State machine control
- TIMERS/COUNTERS
- Digital designs
- Software-Driven Hardware Configuration
