Parameters |
Factory Lead Time |
1 Week |
Package / Case |
900-BBGA, FCBGA |
Operating Temperature |
-40°C~100°C TJ |
Packaging |
Tray |
Series |
Zynq® UltraScale+™ MPSoC EG |
JESD-609 Code |
e1 |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
4 (72 Hours) |
Terminal Finish |
Tin/Silver/Copper (Sn/Ag/Cu) |
HTS Code |
8542.31.00.01 |
Peak Reflow Temperature (Cel) |
NOT SPECIFIED |
Time@Peak Reflow Temperature-Max (s) |
NOT SPECIFIED |
Number of I/O |
204 |
Speed |
533MHz, 600MHz, 1.3GHz |
RAM Size |
256KB |
Core Processor |
Quad ARM® Cortex®-A53 MPCore™ with CoreSight™, Dual ARM®Cortex™-R5 with CoreSight™, ARM Mali™-400 MP2 |
Peripherals |
DMA, WDT |
Connectivity |
CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG |
Architecture |
MCU, FPGA |
Primary Attributes |
Zynq®UltraScale+™ FPGA, 599K+ Logic Cells |
RoHS Status |
ROHS3 Compliant |
This SoC is built on Quad ARM? Cortex?-A53 MPCore? with CoreSight?, Dual ARM?Cortex?-R5 with CoreSight?, ARM Mali?-400 MP2 core processor(s).
This SoC is built on Quad ARM? Cortex?-A53 MPCore? with CoreSight?, Dual ARM?Cortex?-R5 with CoreSight?, ARM Mali?-400 MP2 core processor(s).The manufacturer assigns this system on a chip with a 900-BBGA, FCBGA package as per the manufacturer's specifications.The 256KB RAM implementation of this SoC chip ensures efficient performance for users.The SoC design uses MCU, FPGA architecture for its internal architecture.The system on a chip is part of the series Zynq? UltraScale+? MPSoC EG.As a rule of thumb, the average operating temperature for this SoC meaning should be -40°C~100°C TJ.A significant feature of this SoC security is the combination of Zynq?UltraScale+? FPGA, 599K+ Logic Cells.This SoC system on a chip has been designed in a state-of-the-art Tray package.Total I/Os on this SoC part are 204.
Quad ARM? Cortex?-A53 MPCore? with CoreSight?, Dual ARM?Cortex?-R5 with CoreSight?, ARM Mali?-400 MP2 processor.
256KB RAM.
Built on MCU, FPGA.
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