XPC8260ZUIFBC
| Parameters | |
|---|---|
| Package / Case | 480-LBGA Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | 0°C~105°C TA |
| Packaging | Tray |
| Published | 2004 |
| Series | MPC82xx |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 480 |
| ECCN Code | 5A991 |
| HTS Code | 8542.31.00.01 |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 220 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 1.27mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | PC8260 |
| JESD-30 Code | S-PBGA-B480 |
| Supply Voltage-Max (Vsup) | 1.9V |
| Supply Voltage-Min (Vsup) | 1.7V |
| Speed | 200MHz |
| uPs/uCs/Peripheral ICs Type | MICROPROCESSOR, RISC |
| Core Processor | PowerPC G2 |
| Clock Frequency | 66.66MHz |
| Bit Size | 32 |
| Address Bus Width | 32 |
| Boundary Scan | YES |
| Low Power Mode | NO |
| External Data Bus Width | 64 |
| Format | FLOATING POINT |
| Integrated Cache | YES |
| Voltage - I/O | 3.3V |
| Ethernet | 10/100Mbps (3) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DRAM, SDRAM |
| Additional Interfaces | I2C, SCC, SMC, SPI, UART, USART |
| Co-Processors/DSP | Communications; RISC CPM |
| Height Seated (Max) | 1.65mm |
| Length | 37.5mm |
| RoHS Status | Non-RoHS Compliant |
XPC8260ZUIFBC Description
The XPC8260ZUIFBC PowerQUICC? II? is an advanced integrated communications processor designed for the telecommunications and networking markets. The XPC8260ZUIFBC now offers floating point support.
The XPC8260ZUIFBC PowerQUICC II can best be described as the next generation MPC860 PowerQUICC?, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration. Like the MPC860, the XPC8260ZUIFBC integrates two main components, the embedded G2 core and the Communications Processor Module (CPM).
XPC8260ZUIFBC Features
High-performance, superscalar microprocessor
Disable CPU mode
Supports the NXP? external L2 cache chip (MPC2605)
Improved low-power core
16 Kbyte data and 16 Kbyte instruction cache, four-way set associative
Memory Management Unit
Floating point unit enabled
Common on-chip processor (COP)
System Integration Unit (SIU)
XPC8260ZUIFBC Applications
Communications equipment
Wired networking
Industrial
Electronic point of sale (EPOS)
Personal electronics
PC & notebooks
